? semiconductor components industries, llc, 2005 december, 2005 ? rev. 0 1 publication order number: NB4N11S/d NB4N11S 3.3 v 1:2 anylevel ? input to lvds fanout buffer / translator the NB4N11S is a differential 1:2 clock or data receiver and will accept anylevel tm input signals: lvpecl, cml, lvcmos, lvttl, or lvds. these signals will be translated to lvds and two identical copies of clock or data will be distributed, operating up to 2.0 ghz or 2.5 gb/s, respectively. as such, the NB4N11S is ideal for sonet, gige, fiber channel, backplane and other clock or data distribution applications. the NB4N11S has a wide input common mode range from gnd + 50 mv to v cc ? 50 mv. combined with the 50 internal termination resistors at the inputs, the NB4N11S is ideal for translating a variety of differential or single?ended clock or data signals to 350 mv typical lvds output levels. the NB4N11S is functionally equivalent to the ep11, lvep11, sg11 or 7l11m devices and is offered in a small 3 mm x 3 mm 16?qfn package. application notes, models, and support documentation are available at www.onsemi.com . features ? maximum input clock frequency > 2.0 ghz ? maximum input data rate > 2.5 gb/s ? 1 ps maximum of rms clock jitter ? typically 10 ps of data dependent jitter ? 380 ps typical propagation delay ? 120 ps typical rise and fall times ? functionally compatible with existing 3.3 v lvel, lvep, ep, and sg devices time (58 ps/div) figure 2. typical output waveform at 2.488 gb/s with prbs 2 23?1 (v inpp = 400 mv; input signal ddj = 14 ps) voltage (130 mv/div) device ddj = 10 ps a = assembly location l = wafer lot y = year w = work week *for additional marking information, refer to application note and8002/d. marking diagram* qfn?16 mn suffix case 485g http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ordering information 16 nb4n 11s alyw 1 1 q0 q0 q1 q1 d d v td v td figure 1. logic diagram
NB4N11S http://onsemi.com 2 figure 3. NB4N11S pinout, 16?pin qfn (top view) v cc nc v ee v ee v cc v td d d v td q0 q0 q1 q1 5678 16 15 14 13 12 11 10 9 1 2 3 4 NB4N11S exposed pad (ep) v cc v cc v cc table 1. pin description pin name i/o description 1 q0 lvds output non?inverted d output. typically loaded with 100 receiver termination resistor across differential pair. 2 q0 lvds output inverted d output. typically loaded with 100 receiver termination resistor across differential pair. 3 q1 lvds output non?inverted d output. typically loaded with 100 receiver termination resistor across differential pair. 4 q1 lvds output inverted d output. typically loaded with 100 receiver termination resistor across differential pair. 5 v cc ? positive supply voltage. 6 nc no connect. 7 v ee negative supply voltage. 8 v ee negative supply voltage. 9 v td ? internal 50 termination pin for d . 10 d lvpecl, cml, lvds, lvcmos, lvttl inverted differential clock/data input (note 1). 11 d lvpecl, cml, lvds, lvcmos, lvttl non?inverted differential clock/data input (note 1). 12 v td ? internal 50 termination pin for d . 13 v cc ? positive supply voltage. 14 v cc ? positive supply voltage. 15 v cc ? positive supply voltage. 16 v cc ? positive supply voltage. ep exposed pad. the exposed pad (ep) on the package bottom must be attached to a heat?sinking conduit. the exposed pad may only be electrically connected to v ee . 1. in the dif ferential configuration when the input termination pins(vtd0/vtd0 , vtd1/ vtd1 ) are connected to a common termination voltage or left open, and if no signal is applied on d0/d0 , d1/d1 input, then the device will be susceptible to self?oscillation.
NB4N11S http://onsemi.com 3 table 2. attributes characteristics value moisture sensitivity (note 2) level 1 flammability rating oxygen index: 28 to 34 ul 94 v?0 @ 0.125 in esd protection human body model machine model charged device model > 2 kv > 200 v > 1 kv transistor count 225 meets or exceeds jedec spec eia/jesd78 ic latchup test 2. for additional information, see application note and8003/d. table 3. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply gnd = 0 v 3.8 v v in positive input gnd = 0 v v in v cc 3.8 v i in input current through r t (50 resistor) static surge 35 70 ma ma i osc output short circuit current line?to?line (q to q ) line?to?end (q or q to gnd) q or q to gnd q to q continuous continuous 12 24 ma t a operating temperature range qfn?16 ?40 to +85 c t stg storage temperature range ?65 to +150 c ja thermal resistance (junction?to?ambient) (note 3) 0 lfpm 500 lfpm qfn?16 qfn?16 41.6 35.2 c/w c/w jc thermal resistance (junction?to?case) 1s2p (note 3) qfn?16 4.0 c/w t sol wave solder pb pb?free <3 sec @ 248 c <3 sec @ 260 c 265 265 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 3. jedec standard multilayer board ? 1s2p (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
NB4N11S http://onsemi.com 4 table 4. dc characteristics, clock inputs, lvds outputs v cc = 3.0 v to 3.6 v, gnd = 0 v, t a = ?40 c to +85 c symbol characteristic min typ max unit i cc power supply current (note 8) 35 50 ma differential inputs driven single?ended (figures 11, 12, 16, and 18) v th input threshold reference voltage range (note 7) gnd +100 v cc ? 100 mv v ih single?ended input high voltage v th + 100 v cc mv v il single?ended input low voltage gnd v th ? 100 mv differential inputs driven differentially (figures 7, 8, 9, 10, 17, and 19) v ihd differential input high voltage 100 v cc mv v ild differential input low voltage gnd v cc ? 100 mv v cmr input common mode range (differential configuration) gnd + 50 v cc ? 50 mv v id differential input voltage (v ihd ? v ild ) 100 v cc mv r tin internal input termination resistor 40 50 60 lvds outputs (note 4) v od differential output voltage 250 450 mv v od change in magnitude of v od for complimentary output states (note 9) 0 1 25 mv v os offset voltage (figure 15) 1125 1375 mv v os change in magnitude of v os for complimentary output states (note 9) 0 1 25 mv v oh output high voltage (note 5) 1425 1600 mv v ol output low voltage (note 6) 900 1075 mv note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. lvds outputs require 100 receiver termination resistor between differential pair. see figure 14. 5. v oh max = v os max + ? v od max. 6. v ol max = v os min ? ? v od max. 7. v th is applied to the complementary input when operating in single?ended mode. 8. input termination pins open, d/d at the dc level within v cmr and output pins loaded with r l = 100 across differential. 9. parameter guaranteed by design verification not tested in production.
NB4N11S http://onsemi.com 5 table 5. ac characteristics v cc = 3.0 v to 3.6 v, gnd = 0 v; (note 10) symbo l characteristic ?40 c 25 c 85 c uni t min typ max min typ max min typ max v outpp output voltage amplitude (@ v inppmin )f in 1.0 ghz (figure 4) f in = 1.5 ghz f in = 2.0 ghz 220 200 170 350 300 270 250 200 170 350 300 270 250 200 170 350 300 270 mv f data maximum operating data rate 1.5 2.5 1.5 2.5 1.5 2.5 gb/s t plh , t phl differential input to differential output propagation delay 270 370 470 270 370 470 270 370 470 ps t skew duty cycle skew (note 11) within device skew (note 16) device?to?device skew (note 15) 8 5 30 45 25 100 8 5 30 45 25 100 8 5 30 45 25 100 ps t jitter rms random clock jitter (note 13) f in = 1.0 ghz f in = 1.5 ghz deterministic jitter (note 14) f data = 622 mb/s f data = 1.5 gb/s f data = 2.488 gb/s 0.5 0.5 6 7 10 1 1 20 20 0.5 0.5 6 7 10 1 1 20 20 0.5 0.5 6 7 10 1 1 20 20 ps v inpp input voltage swing/sensitivity (differential configuration) (note 12) 100 v cc ? gnd 100 v cc ? gnd 100 v cc ? gnd mv t r t f output rise/fall times @ 250 mhz q, q (20% ? 80%) 70 120 170 70 120 170 70 120 170 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. measured by forcing v inppmin with 50% duty cycle clock source and v cc ? 1400 mv offset. all loading with an external r l = 100 across ?d? and ?d ? of the receiver. input edge rates 150 ps (20%?80%). 11. see figure 13 differential measurement of t skew = |t plh ? t phl | for a nominal 50% differential clock input waveform @ 250 mhz. 12. input voltage swing is a single?ended measurement operating in differential mode. 13. rms jitter with 50% duty cycle clock signal at 750 mhz. 14. deterministic jitter with input nrz data at prbs 2 23 ?1 and k28.5. 15. skew is measured between outputs under identical transition @ 250 mhz. 16. the worst case condition between q0/q0 and q1/q1 from either d0/d0 or d1/d1 , when both outputs have the same transition. input clock frequency (ghz) figure 4. output voltage amplitude (v outpp ) versus input clock frequency (f in ) and temperature (@ v cc = 3.3 v) output voltage amplitude (mv) 0 50 100 150 200 250 300 350 400 0.5 1 1.5 2 2.5 3 0 85 c ?40 c 25 c
NB4N11S http://onsemi.com 6 time (58 ps/div) figure 5. typical output waveform at 2.488 gb/s with prbs 2 23?1 and oc48 mask (v inpp = 100 mv; input signal ddj = 14 ps) voltage (63.23 mv/div) device ddj = 10 ps r c r c 1.25 k 1.25 k 1.25 k 1.25 k 50 50 dx v tdx v tdx d x figure 6. input structure i
NB4N11S http://onsemi.com 7 gnd v cc gnd lvpecl driver d 50 * z o = 50 z o = 50 50 * d NB4N11S v cc v td gnd v cc gnd cml driver 50 * z o = 50 z o = 50 50 * NB4N11S v cc v td = v td = v cc figure 7. lvpecl interface figure 8. lvds interface v td = v td = v cc ? 2.0 v figure 9. standard 50 load cml interface gnd v cc gnd lvds driver 50 * z o = 50 z o = 50 50 * NB4N11S v cc v td = v td gnd v cc gnd hstl driver 50 * z o = 50 z o = 50 50 * NB4N11S v cc v td = v td = gnd or v dd /2 depending on driver. figure 10. hstl interface gnd v cc gnd lvcmos driver 50 * z o = 50 50 * NB4N11S v cc v td = v td = open d = gnd figure 11. lvcmos interface gnd v cc gnd lvttl driver 50 * z o = 50 50 * NB4N11S v cc v td = open d = gnd figure 12. lvttl interface v td d d v td v td d v td v td v cc d d v td v td d d v td v td d gnd d v td v td d gnd *r tin , internal input termination resistor.
NB4N11S http://onsemi.com 8 figure 13. ac reference measurement d d q q t phl t plh v inpp = v ih (d) ? v il (d) v outpp = v oh (q) ? v ol (q) figure 14. typical lvds termination for output driver and device evaluation driver device receiver device qd q d lvds 100 lvds z o = 50 z o = 50 v ol q n v oh q n v os v od figure 15. lvds output figure 16. differential input driven single?ended d figure 17. differential inputs driven differentially d v th v th d d v ih v il v ihmax v ilmax v ihmin v ilmin v cc v thmax v thmin gnd v th figure 18. v th diagram d d v il v ih(max) v ih v il v ih v il(min) v cmr gnd figure 19. v cmr diagram v inpp = v ihd ? v ild v cc
NB4N11S http://onsemi.com 9 ordering information device package shipping ? NB4N11Smng qfn?16, 3 x 3 mm (pb?free) 123 units / rail NB4N11Smnr2g qfn?16, 3 x 3 mm (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NB4N11S http://onsemi.com 10 package dimensions 16 pin qfn case 485g?01 issue b 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm minimum spacing between lead tip and flag ??? ??? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x e 16x note 5 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k 0.20 ??? l 0.30 0.50 exposed pad mm inches scale 10:1 0.50 0.02 0.575 0.022 1.50 0.059 3.25 0.128 0.30 0.012 3.25 0.128 0.30 0.012 exposed pad *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 NB4N11S/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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